The scaling of VLSI circuits is a constant effort. With circuits becoming smaller and faster, improvement in device driving current is becoming more important. Device current is closely related to gate length, gate capacitance, and carrier mobility. Shortening poly-gate length, increasing gate capacitance, and increasing carrier mobility can improve the device current performance. Reducing gate length in order to shrink circuit size is an on-going effort. Increasing gate capacitance has also been achieved by efforts such as reducing the gate dielectric thickness, increasing the gate dielectric constant, and the like. In order to further improve device current, enhancing carrier mobility has also been explored. Among efforts made to enhance carrier mobility, forming a stressed silicon channel is a known practice. This technique allows the performance of MOS devices to be improved at a constant gate length without adding complexity to circuit fabrication or design.
It has been found that NMOS device performance is improved by tensile stresses in the channel region, while PMOS device performance is improved by compressive stress in the channel region. Stresses can be applied by forming a stressed capping layer, such as a contact etch stop layer (CESL), on an MOS device. FIG. 1 illustrates a conventional CESL scheme for a PMOS device 2 and an NMOS device 4. A compressive stressed CESL 6 is formed over PMOS device 2, while a tensile stressed CESL 8 is formed over NMOS device 4. For CESLs 6 and 8 to have different stresses, typically, two sets of CESL deposition, photolithography and etch processes have to be performed, each forming one of the CESLs 6 and 8. The cost for introducing different stresses is thus high. An additional problem is that conventional CESL films typically use silicon nitride, which has a high dielectric constant. As a result, the RC delay of the resulting integrated circuit is adversely affected.
The related art discloses another method for forming a CESL. The method includes forming a CESL layer having an inherent stress over an NMOS device and a PMOS device, and performing an ion implantation or plasma treatment on the CESL portion over the PMOS device, causing a change of the stress in the CESL portion over the PMOS device. CESL, however, may be formed of various materials, and not all materials respond desirably to plasma treatments. Thus, new methods for forming CESLs, in order to apply beneficial stresses to NMOS and PMOS devices, are needed.